Rxdenq, Rxbca, Unchanged – Cirrus Logic EP93xx User Manual
Page 376
9-74
DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
RXDEnq
Address:
0x8001_009C - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Receive Descriptor Enqueue register. The Receive Descriptor Enqueue
register is used to define the number of valid entries in the descriptor queue.
The register operates as follows: only the Receive descriptor Increment field is
writable and any value written to this field is added to the existing Receive
Descriptor Value. Whenever complete descriptors are read by the MAC, the
Receive Descriptor Value is decremented by the number read. For example, if
the Receive Descriptor Value is 0x07 and the Host writes 03 to the Receive
Descriptor Increment, the new Value will be 0x0A. If the controller then reads
two descriptors, the Value will be 0x08.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
RDV:
Receive Descriptor Value.
RDI:
Receive Descriptor Increment.
RXBCA
Address:
0x8001_0088 - Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RDV
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
RDI
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RBCA
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RBCA