Cirrus Logic EP93xx User Manual
Page 674
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21-18
DS785UM1
Copyright 2007 Cirrus Logic
I
2
S Controller
EP93xx User’s Guide
2
1
2
1
21
Default:
0x0000_0000
Definition:
TX0 Channel Enable
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
i2s_tx0_EN:
TX0 Channel Enable
I2STX1En
Address:
0x8082_0038 - Read/Write
Default:
0x0000_0000
Definition:
TX1 Channel Enable
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
i2s_tx1_EN:
TX1 Channel Enable
I2STX2En
Address:
0x8082_003C - Read/Write
Default:
0x0000_0000
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30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
i2s_tx1_EN
31
30
29
28
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25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
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9
8
7
6
5
4
3
2
1
0
RSVD
i2s_tx2_EN
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