Cirrus Logic EP93xx - Manual (Page 520)

13-24 DS785UM1
Copyright 2007 Cirrus Logic
SDRAM, SyncROM, and SyncFLASH Controller
EP93xx User’s Guide
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When writing to a SyncFLASH device, only single writes
(burst-of-one) are allowed. The value that is written to this
bit specifies that a burst length of either one or four will be
used for Write accesses:
0 - Burst-of-four accesses for both Reads and Writes
1 - Burst-of-one accesses for Writes (SyncFLASH support)
and burst-of-four accesses for Reads
When WBM = ‘1’, the Synchronous Memory controller will
not issue refresh cycles to this domain.
A single word write occurs when the ARM assembly
instruction, ‘str’, is executed. Writing WBM = ‘1’ will not
prevent burst-of-four writes from occurring when the ARM
assembly instruction, ‘stm’, is executed. So, only use
ARM assembly “str” instructions for Write accesses
to SyncFLASH devices.
CasLat: Synchronous memory CAS Latency - Read/Write
The value written to this field specifies the CAS latency
that the Synchronous Memory controller uses for Read or
Write accesses to SDRAM or SyncROM devices:
000 - Reserved
001 - CAS Latency = 2
010 - CAS Latency = 3 (also normal default)
011 - CAS Latency =4
100 - CAS Latency =5 (also default when booting from a
SyncROM device)
101 - CAS Latency =6
110 - CAS Latency = 7
111 - CAS Latency =8
SFConfigAddr: SyncFLASH Configuration register read - Read/Write
The value written to this bit specifies either normal
operation or that the Synchronous Memory controller is
caused to perform a Read access to the Configuration
register that is inside a SyncFLASH device:
0 - Normal operation
1 - Read SyncFLASH Configuration register
The AutoPrecharge bit must be ‘0’ before the
SFConfigAddr bit is written to ‘1’.
2KPAGE: Synchronous memory 2K byte Page - Read/Write