Cirrus Logic EP93xx - Manual (Page 589)

DS785UM1 16-13
Copyright 2007 Cirrus Logic
UART3 With HDLC Encoder
EP93xx User’s Guide
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6
1
6
16
0: Must be written as “0”.
UART3HDLCCtrl
Address:
0x808E_020C - Read/Write
Default:
0x0000_0000
Definition:
HDLC Control Register
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
CMAS: Clock Master:
1 - Transmitter and/or receiver use 1x clock generated by
the internal transmitter.
0 - Transmitter and/or receiver use 1x clock generated
externally.
TXCM: Transmit Clock Mode.
1 - Generate 1x clock when in synchronous HDLC mode
using NRZ encoding.
0 - Do not generate clock.
This bit has no effect unless TXENC is clear and
synchronous HDLC is enabled.
RXCM: Receive Clock Mode.
1 - Use external 1x clock when in synchronous HDLC
mode using NRZ encoding.
0 - Do not use external clock.
This bit has no effect unless RXENC is clear and
synchronous HDLC is enabled.
TXENC: Transmit Encoding method.
1 - Use Manchester bit encoding.
0 - Use NRZ bit encoding.
This bit has no effect unless synchronous HDLC is
enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD CMAS TXCM RXCM TXENC RXENC SYNC TFCEN TABEN RFCEN RILEN RFLEN RTOEN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLAG CRCN CRCApd IDLE AME RSVD RXE TXE TUS CRCE CRCS