Cirrus Logic EP93xx User Manual
Page 698
22-10
DS785UM1
Copyright 2007 Cirrus Logic
AC’97 Controller
EP93xx User’s Guide
2
2
2
2
22
AC97TXCRx
Address:
AC97TXCR1 - 0x8088_0008 - Read/Write
AC97TXCR2 - 0x8088_0028 - Read/Write
AC97TXCR3 - 0x8088_0048 - Read/Write
AC97TXCR4 - 0x8088_0068 - Read/Write
Definition:
Transmit Control Registers. The AC97TXCR registers are read/write. The data
contained within the register controls the data slots that are contained within
the FIFO’s transmit register. The data within this FIFO must be of the same
sampling frequency, such as all audio slot data at 44.1 kHz. This register is
used to create slot 0 for transmitting. If this register specifies that the data
within is for Slot1 and 2, this will take precedence over the data in the
SLOT1TX and SLOT2TX register. If Slot 1 and 2 data is to be sent via this
FIFO, it will always be transmitted at 48kHz. Therefore, it is advisable not to
enable any other slots unless they too are sampled at 48kHz.
The data contained within the TSIZE bits controls the number of zeros that are
to be appended to data to make it 20 bits.
Should two channels be enabled for the same data slot, then data is taken
from/given to the lower channel number.
The data into the FIFO is stored in the lowest slot first. For example if the FIFO
is set up to store in slots 3 and 4, then slot 3 is the first data into the FIFO and
slot 4 the second.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
FDIS:
FIFO Disable
0 - The FIFO buffers are Enabled (FIFO mode).
1 - The FIFO is disabled (character mode). That is, the
FIFO becomes 1-byte-deep holding registers.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
FDIS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CM
TSIZE
TX12
TX11
TX10
TX9
TX8
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TEN