Cirrus Logic EP93xx User Manual
Page 150
5-24
DS785UM1
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
5
5
DMA_ENFIQ:
When set the arbiter will degrant DMA from the AHB bus
and will ignore subsequent requests from DMA if an FIQ is
active. When FIQ is cleared the DMA request is allowed
again. There is no impact on other masters. Reset to 0.
USH_ENIRQ:
When set the arbiter will degrant USB host from the AHB
bus and will ignore subsequent requests from the USB
Host if an IRQ is active. When IRQ is cleared, the USB
Host request is allowed again. There is no impact on other
masters. Reset to 0.
USH_ENFIQ:
When set the arbiter will degrant USB Host from the AHB
bus and will ignore subsequent requests from USB Host if
an FIQ is active. When FIQ is cleared, the USB Host
request is allowed again. There is no impact on other
masters. Reset to 0.
MAC_ENIRQ:
When set the arbiter will degrant Ethernet MAC from the
AHB bus and will ignore subsequent requests from the
MAC if an IRQ is active. When IRQ is cleared, the MAC
request is allowed again. There is no impact on other
masters. Reset to 0.
MAC_ENFIQ:
When set the arbiter will degrant the Ethernet MAC from
the AHB bus and will ignore subsequent requests from the
MAC if an FIQ is active. When FIQ is cleared, the MAC
request is allowed again. There is no impact on other
masters. Reset to 0.
BootModeClr
Address:
0x8093_0058 - Write Only
Definition:
The BootModeClr register is a write-to-clear register. Reset activates the boot
ROM remap function causing the internal boot ROM to map to address zero, if
internal boot is selected. Writing BootModeClr removes the internal ROM
address remap, restoring normal address space.
Bit Descriptions:
RSVD:
There are no readable bits in this register.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD