Cirrus Logic EP93xx User Manual
Page 346
9-44
DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
IAHA:
Individual Address Hash Accept. When set, received
frame are accepted when the DA is an Individual Address
(first bit of DA = 0), that is accepted by the hash table. See
Descriptor Processor Transmit Registers.
IA3:
Individual Accept 3. When set, received frames are
accepted which the DA matches the Individual Address 3
Register.
IA2:
Individual Accept 2. When set, received frames are
accepted which the DA matches the Individual Address 2
Register.
IA1:
Individual Accept 1. When set, received frames are
accepted which the DA matches the Individual Address 1
Register.
IA0:
Individual Accept 0. When set, received frames are
accepted which the DA matches the Individual Address 0
Register.
Note: It may become necessary for the host to change the destination address filter criteria and
NOT go through a controller reset. This can be done. The host should:
1. Clear SerRxON (RXCtl) to prevent an additional received frame while the filters are
being changed.
2. Modify the destination filter bits in this register.
3. Modify the Logical Address Filter, if necessary.
4. Modify the Individual Address Filter, if necessary.
5. Set SerRxON to re-enable the receiver.
When the host changes the destination filter, it is possible that a frame will be missed while
SerRxON is clear.
TXCtl
Address:
0x8001_0004 - Read/Write
Chip Reset:
0x0000_0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
DefDis
MBE
ICRC
TxPD
OColl
SP
PB
STxON