Vclkstrtstop – Cirrus Logic EP93xx User Manual
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Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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VClkStrtStop
Address: 0x8003_000C
Default: 0x0000_0000
Definition: Vertical Clock Start/Stop register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
STOP:
Stop - Read/Write
The STOP timing register contains the value of the Vertical
down counter at which the VCLKEN signal goes inactive
(stops). This indicates the end of the video clock for the
Vertical frame. Please refer to video signalling timing
diagrams in
. VCLKEN is an
internal block signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
STRT:Start - Read/Write
The STRT timing register contains the value of the Vertical
down counter at which the VCLKEN signal becomes
active (starts). This indicates the start of the video clock for
the Vertical frame. Please refer to video signalling timing
diagrams in
. VCLKEN is an
internal block signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
STOP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
STRT