Vsigstrtstop – Cirrus Logic EP93xx User Manual
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Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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CLKEN:
Clock Enable - Read/Write
Writing a ‘1’ to this bit enables the CLKEN control for
calculation in the video signature.
Writing a ‘0’ to this bit disables the CLKEN control for
calculation in the video signature.
BLANK:
Blank - Read/Write
Writing a ‘1’ to this bit enables the BLANK output for
calculation in the video signature.
Writing a ‘0’ to this bit disables the BLANK output for
calculation in the video signature.
HSYNC:
Horizontal Synchronization - Read/Write
Writing a ‘1’ to this bit enables the HSYNC output for
calculation in the video signature.
Writing a ‘0’ to this bit disables the HSYNC output for
calculation in the video signature.
VSYNC:
Vertical Synchronization - Read/Write
Writing a ‘1’ to this bit enables the VSYNC output for
calculation in the video signature.
Writing a ‘0’ to this bit disables the VSYNC output for
calculation in the video signature.
PEN:
Pixel Bits Enable - Read/Write
Writing ‘1’s to these bits enables respective pixel bits for
calculation in the video signature.
Writing ‘0’s to these bits disables respective pixel bits for
calculation in the video signature.
VSigStrtStop
Address: 0x8003_0208
Default: 0x0000_0000
Definition: Vertical Signature Bounds Start/Stop register
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RSVD
STOP
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0
RSVD
STRT