Cirrus Logic EP93xx - Manual (Page 664)

21-8 DS785UM1
Copyright 2007 Cirrus Logic
I 2 S Controller
EP93xx User’s Guide
2
1
2
1
21
order to generate a set of audio clocks, LRCK (word clock) and SCLK (bit clock). The control
bits required are:
• Master Mode Enable. (i2s_mstr_clk_cfg[0])
• Word Length Control (i2s_mstr_clk_cfg[2:1])
• Bit Clock Polarity (i2s_mstr_clk_cfg[3])
• Not Bit Clock Gating (i2s_mstr_clk_cfg[4]).
• Bit Clock Rate (i2s_mstr_clk_cfg[6:5])
These control bits come from the TX and the RX clock configuration registers and the word
length registers. This control is sent out through the i2s_mstr_clk_cfg port of the I
2
S controller
to the audio clock generator. The audio clock generator responds with the correct clock
definition based on the settings received.
If both the TX and RX are required to be in master mode at the same time, both the RX and
TX share the same master audio clocks. The following shows how i2s_mstr_clk_cfg is
generated.
• If the Transmitter is enabled, the clock configuration information will always come from
I2STXClkCfg register. Therefore, the I2SRXClkCfg (receiver clock configuration) register
must be configured to be the same as the I2STXClkCfg (transmitter clock configuration)
register in order to ensure correct operation of the receiver. The word lengths for both
the TX and RX must be the same.
• If the Transmitter is disabled and the Receiver is required to be in master mode, then the
i2s_mstr_clk_cfg output is generated from the I2SRXClkCfg register and the RX word
length register.
Please note, the I2SClkDiv (Addr=0x8093_008C) register in the SYSCON block has an effect
on I
2
S clock generation as well. The details are listed in Table 21-4 . The controlling bit field
for each function is determined by the ORIDE bit in the I2SClkDiv register (I2SClkDiv[29]).
This table does not show the details of how to control this function. Please refer to each
individual block for a detailed description.
Table 21-4. I2SClkDiv SYSCON Register Effect on I 2 S Clock Generation
Function ORIDE=1 ORIDE=0
SCLK polarity SPOL (I2SClkDiv[19]) i2s_mstr_clk_cfg[3]
SCLK Speed and
Gating DROP(I2SClkDiv[20]),
SDIV(I2SClkDiv[16])
SCLK always is MCLK/2.
SCLK is gated when
i2s_mstr_clk_cfg[4]=0,
i2s_mstr_clk_cfg[6:5]=0 and
i2s_mstr_clk_cfg[2:1]=1, otherwise,
SCLK is not gated.
LRCK Speed LRDIV(I2SClkDiv[18:17]) i2s_mstr_clk_cfg[6:5]
Audio Slave Mode SLAVE(I2SClkDiv[30]) i2s_mstr_clk_cfg[0]
Audio Clock
(SCLK, LRCLK)
Generation Enable
SENA(I2SClkDiv[31])
I2SonAC97 (DeviceCfg[6]) or
I2SonSSP (DeviceCfg[7]). If either
one is set, it enables the clock
generation.