Cirrus Logic EP93xx - Manual (Page 803)

DS785UM1 28-13
Copyright 2007 Cirrus Logic
GPIO Interface
EP93xx User’s Guide
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The INTTYPE1 register controls what type of INTERRUPT can occur on Port A/B/F. Level
sensitive when “0” is written to a bit location (“0” default on reset), edge sensitive when “1” is
written to a bit location (the type of edge/level is controlled by the INTTYPE2 register). The
user must make sure that the direction of port A/B/F is set to input and the corresponding bit
in the GPIO INTERRUPT ENABLE register is set to allow the interrupt.
All bits are cleared by a system reset.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
PxINTE: Determines which type of interrupt may occur.
GPIOxIntType2
Address:
GPIOAIntType2: 0x8084_0094 - Read/Write
GPIOBIntType2: 0x8084_00B0 - Read/Write
GPIOFIntType2: 0x8084_0050 - Read/Write
Definition:
The GPIOxINTTYPE2 registers controls the type of edge/level sensitive interrupt that can
occur on the bits in Ports A/B/F.
The interrupt is rising edge or high level sensitive if a “1” is written to the corresponding bit in
GPIOxINTTYPE2 and falling edge or low level sensitive if a “0” is written to the corresponding
bit in GPIOxINTTYPE2. The user must make sure that the direction of port A/B/F is set to
input and the corresponding bits in the GPIO Interrupt Enable register and GPIOxINTTYPE1
are set correctly in order for this register to have any effect. For edge sensitive interrupts the
GPIOxINTTYPE1 bit should set high and low for level sensitive interrupts.
All bits are cleared by a system reset.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
PxINTR: Determines which type of edge or level sensitive interrupt
may occur.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD PxINTR