Cirrus Logic EP93xx - Manual (Page 57)

DS785UM1 2-19
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2
2
2
0x8001_0090 RXDQBAdd MAC Receive Descriptor Queue Base Address Register N
0x8001_0094 RXDQBLen MAC Receive Descriptor Queue Base Length Register N
0x8001_0096 RXDQCurLen MAC Receive Descriptor Queue Current Length Register N
0x8001_0098 RXDCurAdd MAC Receive Descriptor Current Address Register N
0x8001_009C RXDEnq MAC Receive Descriptor Enqueue Register N
0x8001_00A0 RXStsQBAdd MAC Receive Status Queue Base Address Register N
0x8001_00A4 RXStsQBLen MAC Receive Status Queue Base Length Register N
0x8001_00A6 RXStsQCurLen MAC Receive Status Queue Current Length Register N
0x8001_00A8 RXStsQCurAdd MAC Receive Status Queue Current Address Register N
0x8001_00AC RXStsEnq MAC Receive Status Enqueue Register N
0x8001_00B0 TXDQBAdd MAC Transmit Descriptor Queue Base Address Register N
0x8001_00B4 TXDQBLen MAC Transmit Descriptor Queue Base Length Register N
0x8001_00B6 TXDQCurLen MAC Transmit Descriptor Queue Current Length Register N
0x8001_00B8 TXDQCurAdd MAC Transmit Descriptor Current Address Register N
0x8001_00BC TXDEnq MAC Transmit Descriptor Enqueue Register N
0x8001_00C0 TXStsQBAdd MAC Transmit Status Queue Base Address Register N
0x8001_00C4 TXStsQBLen MAC Transmit Status Queue Base Length Register N
0x8001_00C6 TXStsQCurLen MAC Transmit Status Queue Current Length Register N
0x8001_00C8 TXStsQCurAdd MAC Transmit Status Queue Current Address Register N
0x8001_00D0 RXBufThrshld MAC Receive Buffer Threshold Register N
0x8001_00D4 TXBufThrshld MAC Transmit Buffer Threshold Register N
0x8001_00D8 RXStsThrshld MAC Receive Status Threshold Register N
0x8001_00DC TXStsThrshld MAC Transmit Status Threshold Register N
0x8001_00E0 RXDThrshld MAC Receive Descriptor Threshold Register N
0x8001_00E4 TXDThrshld MAC Transmit Descriptor Threshold Register N
0x8001_00E8 MaxFrmLen MAC Maximum Frame Length Register N
0x8001_00EC RXHdrLen MAC Receive Header Length Register N
0x8001_0100 - 0x8001_010C Reserved
0x8001_4000 - 0x8001_50FF MACFIFO MAC FIFO RAM N
0x8002_xxxx USB USB Registers N
0x8002_0000 HcRevision USB Host Controller Revision N
0x8002_0004 HcControl USB Host Controller Control N
0x8002_0008 HcCommandStatus USB Host Controller Command Status N
0x8002_000C HcInterruptStatus USB Host Controller Interrupt Status N
0x8002_0010 HcInterruptEnable USB Host Controller Interrupt Enable N
0x8002_0014 HcInterruptDisable USB Host Controller Interrupt Disable N
0x8002_0018 HcHCCA USB Host Controller HCCA N
0x8002_001C HcPeriodCurrentED USB Host Controller Period CurrentED N
0x8002_0020 HcControlHeadED USB Host Controller Control HeadED N
0x8002_0024 HcControlCurrentED USB Host Controller Control CurrentED N
0x8002_0028 HcBulkHeadED USB Host Controller Bulk HeadED N
0x8002_002C HcBulkCurrentED USB Host Controller Bulk CurrentED N
Table 2-8. Internal Register Map (Continued)
Address Register Name Register Description
SW
Lock