Cirrus Logic EP93xx User Manual
Page 439
DS785UM1
10-45
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
1
0
1
0
10
Address:
0x8000_03C0 - Read/Write
Definition:
DMA Global Interrupt Register. This register indicates which channels have an
active interrupt. It is a read only register.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
D0 - D1:
These interrupts are per channel interrupts, as shown in
. Each bit is a logical OR of the INTERRUPT
register per channel. There are no dedicated storage of
these channel interrupts. Once each Channel’s Interrupts’
are clear, the associated channel interrupt is clear.
Note: The order of the internal M2P channel interrupts is
for compatibility reasons with previous versions of
software.
DMAChArb
Address:
0x8000_0380 - Read/Write
Table 10-10. DMA Global Interrupt (DMAGlInt) Register
Bit No.
Description
D[31:12]
RSVD
D11
M2M Channel 1 Interrupt
D10
M2M Channel 0 Interrupt
D9
M2P Channel 8 Interrupt
D8
M2P Channel 9 Interrupt
D7
M2P Channel 6 Interrupt
D6
M2P Channel 7 Interrupt
D5
M2P Channel 4 Interrupt
D4
M2P Channel 5 Interrupt
D3
M2P Channel 2 Interrupt
D2
M2P Channel 3 Interrupt
D1
M2P Channel 0 Interrupt
D0
M2P Channel 1 Interrupt
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
CHARB