Cirrus Logic EP93xx User Manual
Page 234
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DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
7
DHORZ:
Double Horizontal - Read/Write
Writing DHORZ = ‘1’ forces the values of the defined bit-
fields in the
, and
registers to be doubled
(2X programmed value) when used.
0 - Disable
1 - Enable
EQUSER:
Equalization/Serration - Read/Write
If SYNCEN = ‘1’ and CSYNC = ‘1’ (both defined below),
writing EQUSER = ‘1’ forces equalization and serration
pulses to be inserted into the composite synchronization
signal on the V_CSYNC pin.
0 - Disable
1 - Enable
INTRLC:
Interlace - Read/Write
Writing INTRLC = ‘1’ enables interlaced frame timing.
0 - Disable
1 - Enable
INT:
Interrupt - Read/Write
If INTEN = ‘1’, an INT = ‘1’ status indicates that the end of
active video interrupt has occurred.
0 - No interrupt
1 - Interrupt occurred
Write “0” to clear, write “1” to test.
INTEN:
Interrupt Enable - Read/Write
Writing INTEN = ‘1’ enables the end of active video
interrupt.
0 - Disable
1 - Enable
PIFEN:
Parallel Interface Enable - Read/Write
0 - Enable interface for normal display operation
1 - Enable interface for Smart Panel operation
Writing PIFEN = ‘1’ redefines the signals on these pins for
Smart Panel operation: