Cirrus Logic EP93xx - Manual (Page 588)

16-12 DS785UM1
Copyright 2007 Cirrus Logic
UART3 With HDLC Encoder
EP93xx User’s Guide
1
6
1
6
16
Default:
0x0000_0000
Definition:
UART3 DMA Control Register
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
DMAERR: RX DMA error handing enable. If 0, the RX DMA interface
ignores error conditions in the UART receive section. If 1,
the DMA interface stops and notifies the DMA block when
an error occurs. Errors include break errors, parity errors,
and framing errors.
TXDMAE: TX DMA interface enable. Setting to 1 enables the private
DMA interface to the transmit FIFO.
RXDMAE: RX DMA interface enable. Setting to 1 enables the private
DMA interface to the receive FIFO.
UART3ModemCtrl
Address:
0x808E_0100 - Read/Write
Default:
0x0000_0000
Definition:
Modem Control Register. Only the OUT1 and OUT2 bits have functionality in
UART3. The RTS and DTR bits exist but have no function.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
OUT2: OUT2 function. Controls the TENn output behavior:
1 = TENn is driven by the UART3Flag.BUSY status bit;
that is, TENn is low whenever the UART has transmit data
to send.
0 = TENn is controlled by the OUT1 bit.
OUT1: OUT1 function. When OUT2 = “0”, then TENn = OUT1.
Otherwise OUT1 is ignored.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD 0 RSVD OUT2 OUT1 RSVD