Cirrus Logic EP93xx - Manual (Page 632)

17-36 DS785UM1
Copyright 2007 Cirrus Logic
IrDA
EP93xx User’s Guide
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RFS: Receive buffer Service Request (read only).
0 - Receive buffer is empty or the receiver is discarding
data or the receiver is disabled.
1 - Receive buffer is not empty and the receiver is
enabled, DMA service request signaled.
The bit is automatically cleared when the receive buffer is
emptied.
TAB: Transmit Frame Aborted. Set to “1” when a transmitted
frame is terminated with an abort. This will only occur if the
TUS bit is set in the IrCtrl register. The bit is cleared by
writing a “1” to this bit.
TFC: Transmitted Frame Complete. Set to “1” whenever a
transmitted frame completes (whether it is terminated with
a CRC followed by a stop flag or terminated with an abort).
This bit is cleared by writing a “1” to this bit.
TFS: Transmit buffer Service Request (read only).
0 - Transmit buffer is full or transmitter disabled.
1 - Transmit buffer is not full and the transmitter is
enabled, DMA service is signaled.
The bit is automatically cleared after the buffer is filled.
FIMR
Address:
0x808B_0184 - Read/Write
Default:
0x0000_0000
Definition:
FIR Interrupt Mask Register.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
RFL: RFL mask bit. When high, the FIR RFL status can
generate an interrupt.
RIL: RIL mask bit. When high, the FIR RIL status can generate
an interrupt.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RFL RIL RFC RFS TAB TFC TFS