Cirrus Logic EP93xx - Manual (Page 571)

DS785UM1 15-13
Copyright 2007 Cirrus Logic
UART2
EP93xx User’s Guide
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SIRLP: SIR Low Power Mode. This bit selects the IrDA encoding
mode. If this bit is cleared to 0, low level bits are
transmitted as an active high pulse with a width of 3/16
th
of
the bit period. If this bit is set to “1”, low level bits are
transmitted with a pulse width which is 3 times the period
of the IrLPBaud16 input signal, regardless of the selected
bit rate. Setting this bit uses less power, but may reduce
transmission distances.
SIREN: SIR Enable. If this bit is set to “1”, the IrDA SIR
encoder/decoder is enabled. This bit has no effect if the
UART is not enabled by bit 0 being set to “1”. When the
IrDA SIR encoder/decoder is enabled, data is transmitted
and received on nSIROUT and SIRIN. UARTTXD remains
in the marking state (set to “1”). Signal transitions on
UARTRXD or modem status inputs will have no effect.
When the IrDA SIR encoder/decoder is disabled,
nSIROUT remains cleared to 0 (no light pulse generated),
and signal transitions on SIRIN will have no effect.
UARTE: UART Enable. If this bit is set to “1”, the UART is enabled.
Data transmission and reception occurs for UART signals.
UART2Flag
Address:
0x808D_0018 - Read/Write
Default:
0x0000_0000
Definition:
UART Flag Register
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
TXFE: Transmit FIFO Empty. The meaning of this bit depends on
the state of the FEN bit in the UART2LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the transmit
holding register is empty. If the FIFO is enabled, the TXFE
bit is set when the transmit FIFO is empty.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD TXFE RXFF TXFF RXFE BUSY DCD DSR CTS