Vlinestotal, Vsyncstrtstop, Vertical frame timing registers vlinestotal – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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Vertical Frame Timing Registers
VLinesTotal
Address: 0x8003_0000
Default: 0x0000_0000
Definition: Total horizontal lines that compose a vertical frame
Bit Descriptions:
RSVD:
Reserved - Unknown during read
TOTAL:
VLines Total - Read/Write
The VLines Total value written to this field specifies the
total number of horizontal lines for a video frame including
synchronization, blanking, and active lines. This value is
used to preset the Vertical down counter. Please refer to
video the signalling timing diagrams shown in
and
.
VSyncStrtStop
Address: 0x8003_0004
Default: 0x0000_0000
Definition: Vertical Sync Pulse Start/Stop register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
STOP:
Stop - Read/Write
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RSVD
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1
0
RSVD
TOTAL
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RSVD
STOP
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1
0
RSVD
STRT