Cirrus Logic EP93xx - Manual (Page 305)

DS785UM1 9-3
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
The RAM blocks are interleaved in the AHB address space. AHB address bits 0 and 1 are
byte selects and must be zero for direct access. AHB address bit 2 selects the left or right
RAM array, which is the Transmit or Receive array. AHB address bits 3,4, and 5 perform a 1-
of-8 column select. Address bit 6 selects the even or odd row address. Address bits 7, 8, 9,
and 10 decode the rows. Thus from an AHB addressing perspective, the MAC FIFOs are one
large RAM array.
Table 9-1 defines the FIFO RAM address map as it appears in the address space. Address
are in byte units. All data transfers to the FIFO RAM are restricted to words.
Caution: Accessing the FIFO RAM while the MAC is operating will likely cause a
malfunction.
There is no arbitration logic between direct AHB access and MAC Descriptor Processor
access.
The MAC configurations registers and FIFO RAMs are only word accessible
9.1.2 MAC Engine
The MAC engine is compliant with the requirements of ISO/IEC 8802-3 (1993), Sections 3
and 4.
9.1.2.1 Data Encapsulation
In transmission, the MAC automatically prepends the preamble, and computes and appends
the FCS. The data after the SFD and before the FCS is supplied by the host as the
transmitted data. FCS generation by the MAC may be disabled by setting InhibitCRC bit in
the Transmit Frame Descriptor. Refer to
Figure 9-2 .
Table 9-1. FIFO RAM Address Map
FIFO RAM Address Map Usage
0x8001_4000 to 0x8001_47FF Rx Data
0x8001_4800 to 0x8001_4FFF Tx Data
0x8001_5000 to 0x8001_503F Rx Status
0x8001_5040 to 0x8001_507F Tx Status
0x8001_5080 to 0x8001_50BF Rx Descriptor
0x8001_50C0 to 0x8001_50FF Tx Descriptor