Cirrus Logic EP93xx - Manual (Page 8)

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Copyright 2007 Cirrus Logic, Inc. DS785UM1
EP93xx User’s Guide
Chapter 10. DMA Controller................................................................................ 10-1
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.1.1 DMA Features List.......................................................................................................10-1
10.1.2 Managing Data Transfers Using a DMA Channel .......................................................10-2
10.1.3 DMA Operations ..........................................................................................................10-3
10.1.3.1 Memory-to-Memory Channels ...................................................................10-3
10.1.3.2 Memory-to-Peripheral Channels ................................................................10-4
10.1.4 Internal M2P or P2M AHB Master Interface Functional Description............................10-4
10.1.5 M2M AHB Master Interface Functional Description.....................................................10-5
10.1.5.1 Software Trigger Mode ..............................................................................10-5
10.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP and IDE) and
for External Peripherals without Handshaking Signals ...........................................10-6
10.1.5.3 Hardware Trigger Mode for External Peripherals with
Handshaking Signals ................................................................................................10-6
10.1.6 AHB Slave Interface Limitations ..................................................................................10-6
10.1.7 Interrupt Interface ........................................................................................................10-6
10.1.8 Internal M2P/P2M Data Unpacker/Packer Functional Description ..............................10-6
10.1.9 Internal M2P/P2M DMA Functional Description ..........................................................10-7
10.1.9.1 Internal M2P/P2M DMA Buffer Control Finite State Machine ....................10-7
10.1.9.2 Data Transfer Initiation and Termination ...................................................10-9
10.1.10 M2M DMA Functional Description ...........................................................................10-10
10.1.10.1 M2M DMA Control Finite State Machine ...............................................10-10
10.1.10.2 M2M Buffer Control Finite State Machine ..............................................10-12
10.1.10.3 Data Transfer Initiation ..........................................................................10-13
10.1.10.4 Data Transfer Termination .....................................................................10-15
10.1.10.5 Memory Block Transfer..........................................................................10-16
10.1.10.6 Bandwidth Control .................................................................................10-16
10.1.10.7 External DMA Request (DREQ) Mode ..................................................10-16
10.1.11 DMA Data Transfer Size Determination ..................................................................10-17
10.1.11.1 Software Initiated M2M and M2P/P2M Transfers ..................................10-17
10.1.11.2 Hardware-Initiated M2M Transfers ........................................................10-18
10.1.12 Buffer Descriptors....................................................................................................10-18
10.1.12.1 Internal M2P/P2M Channel Rx Buffer Descriptors ................................10-19
10.1.12.2 Internal M2P/P2M Channel Tx Buffer Descriptors.................................10-19
10.1.12.3 M2M Channel Buffer Descriptors...........................................................10-19
10.1.13 Bus Arbitration .........................................................................................................10-19
10.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-20
10.2.1 DMA Controller Memory Map ....................................................................................10-20
10.2.2 Internal M2P/P2M Channel Register Map .................................................................10-21
Chapter 11. Universal Serial Bus Host Controller ............................................ 11-1
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
11.1.1 Features ......................................................................................................................11-1
11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
11.2.1 Data Transfer Types....................................................................................................11-2
11.2.2 Host Controller Interface..............................................................................................11-3
11.2.2.1 Communication Channels..........................................................................11-3
11.2.2.2 Data Structures..........................................................................................11-4
11.2.3 Host Controller Driver Responsibilities ........................................................................11-6
11.2.3.1 Host Controller Management .....................................................................11-6
11.2.3.2 Bandwidth Allocation .................................................................................11-6
11.2.3.3 List Management .......................................................................................11-7
11.2.3.4 Root Hub....................................................................................................11-7