Cirrus Logic EP93xx - Manual (Page 399)

DS785UM1 10-5
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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occurred. If the ICE bit is not set, then the DMA flushes the last good data out to memory and
terminates the transfer for the current buffer. Where whole words are present in the packer,
word transfers are used. For the remaining bytes (up to a maximum of 3), byte transfers are
used. Thus the maximum number of bus transfers performed to empty the packer is 6, that is,
3 word transfers and 3 byte transfers.
If the number of bytes transferred from a receive peripheral reaches the MaxTransfer count
then this has the same effect as the RxEnd signals being asserted by the peripheral. The
DMA controller asserts RxTC to the peripheral to indicate this condition.
The end of the transfer is signalled by the transfer count being reached, or by the peripheral.
In the latter case, any data remaining in a packer unit is written to memory. Any data in an un-
packer unit is considered invalid, and therefore discarded, as is data remaining in the transmit
FIFO.
When a peripheral receive transfer is complete any data in the packer unit is written to
memory. The data may not form a complete quad-word. If an incomplete quad-word is
present, data is transferred to memory in either word or byte accesses. The number of valid
bytes remaining to be transferred is used to control the type of access. If the number of bytes
is 16, then a normal quad word write is performed. If the number of bytes is more than 4, then
word accesses are performed until the number of bytes is less than 4. If the number of bytes
is less than 4, then byte accesses are performed until the remainder of the data has been
transferred.
If the peripheral ended the transfer with an error code, an interrupt is generated, and
operation continues as normal using the next buffer descriptor (if it has been set up) to
ensure that a minimal amount of data is lost. The point at which the transfer failed can be
determined by reading the channel current address register for the last buffer. An example of
an internal peripheral error code is the Transmit FIFO underflow error in the AAC.
10.1.5 M2M AHB Master Interface Functional Description
The AHB Master interface is also used to transfer data between either the system memory or
external peripheral and the DMA Controller M2M channels in both receive and transmit
directions.
10.1.5.1 Software Trigger Mode
When a M2M channel receives a software trigger and the buffer descriptor has been
programmed, the AHB master interface begins to read data from memory into the data bay.
When the DMA_MEM_RD state is exited (that is, data transfer to the data bay has finished)
this causes the AHB master interface to write the data contained in the data bay to main
memory. The data may not form a complete quad-word. If an incomplete quad-word is
present, data is transferred to memory in either word or byte accesses. The number of valid
bytes remaining to be transferred is used to control the type of access. If the number of bytes
is 16, then a normal quad word write is performed. If the number of bytes is more than 4, then
word accesses are performed until the number of bytes is less than 4. If the number of bytes
is less than 4, then byte accesses are performed until the remainder of the data has been
transferred.