Cirrus Logic EP93xx - Manual (Page 684)

21-28 DS785UM1
Copyright 2007 Cirrus Logic
I 2 S Controller
EP93xx User’s Guide
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i2s_rx_bcr: RX bit clock rate.
00 - I2SRXClkCfg[4] defines the bit clock generation.
01 - Bit clock rate is fixed at 32x. Word length is ignored.
10 - Bit clock rate is fixed at 64x. Word length is ignored.
11 - Bit clock rate is fixed at 128x. Word length is ignored.
i2s_rx_nbcg: Defines RX not bit clock gating mode.
If I2SRXClkCfg[5:6] = 00, this bit defines the bit clock rate,
otherwise ignored.
Bit clock rate = 32x if word length is 16.
Bit clock rate = 64x if word length is 32.
Bit clock rate = 64x if word length is 24.
There is a special case when the word length is 24.
If this bit = 0 and the word length is 24, the last 8 cycles
are gated off in each word.
If this bit = 1 and the word length is 24, the last 8 cycles
are not gated off in each word.
i2s_mstr: Defines if the RX Audio clocks are slave or master.
0 - slave mode.
1 - master mode.
i2s_rrel: Determines the timing of the lrckr with respect to the sdix
data inputs.
0 - Transition of lrckr occurs together with the first data bit.
1 - Transition of lrckr occurs one bitclk cycle before the first
sdix data bit.
i2s_rckp: Defines polarity of the RX bitclk.
1 - Positive clock polarity. The lrckr and sdix lines change
synchronously with the positive edge of the bitclk and are
considered valid during negative transitions.
0 - Negative clock polarity. The lrckr and sdix lines change
synchronously with the negative edge of the bitclk and are
considered valid during positive transitions.
i2s_rlrs: Defines the polarity or lrckr.
0 - if lrckr is low then it is the left word, if lrckr is high then it
is the right word.
1 - if lrckr is low then it is the right word, if lrckr is high then
it is the left word.