Cirrus Logic EP93xx - Manual (Page 6)

vi
©
Copyright 2007 Cirrus Logic, Inc. DS785UM1
EP93xx User’s Guide
7.4.8.6 FRAME_CNTx timing ..................................................................................7-16
7.4.8.7 Grayscale Look-Up Table (GrySclLUT) .......................................................7-17
7.4.8.8 GrySclLUT Timing Diagram .........................................................................7-18
7.4.9 Hardware Cursor ...........................................................................................................7-24
7.4.9.1 Registers Used for Cursor ...........................................................................7-26
7.4.10 Video Timing................................................................................................................7-28
7.4.10.1 Setting the Video Memory Parameters......................................................7-31
7.4.10.2 PixelMode ..................................................................................................7-32
7.4.11 Blink Logic ...................................................................................................................7-32
7.4.11.1 BlinkRate ...................................................................................................7-32
7.4.11.2 Defining Blink Pixels ..................................................................................7-32
7.4.11.3 Types of Blinking .......................................................................................7-33
7.4.12 Color Mode Definition ..................................................................................................7-35
7.4.12.1 Pixel Look-up Table Mode .........................................................................7-35
7.4.12.2 Triple 8-bit Color Definition Mode ..............................................................7-35
7.4.12.3 16-bit 565 Color Definition Mode ...............................................................7-35
7.4.12.4 16-bit 555 Color Definition Mode ...............................................................7-35
7.5 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-36
Chapter 8. Graphics Accelerator.......................................................................... 8-1
8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.2 Block Processing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.2.1 Copy ................................................................................................................................8-2
8.2.1.1 Transparency.................................................................................................8-2
8.2.1.2 Logical Mask..................................................................................................8-2
8.2.1.3 Logical Destination ........................................................................................8-2
8.2.1.4 Operation Precedence ...................................................................................8-2
8.2.2 Remapping ......................................................................................................................8-3
8.2.3 Block Fills ........................................................................................................................8-3
8.2.4 Packed Memory Transfer ................................................................................................8-3
8.3 Line Draws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3
8.3.1 Breshenham Line Draws .................................................................................................8-4
8.3.2 Pixel Step Line Draws .....................................................................................................8-4
8.4 Memory Organization for Graphics Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
8.4.1 Memory Organization for 1 Bit Per Pixel (bpp) ...............................................................8-5
8.4.2 Memory Organization for 4-Bits Per Pixel .......................................................................8-5
8.4.3 Memory Organization for 8-Bits Per Pixel .......................................................................8-5
8.4.4 Memory Organization for 16-Bits Per Pixel .....................................................................8-6
8.4.5 Memory Organization for 24-Bits Per Pixel .....................................................................8-7
8.4.6 Memory Map Access .......................................................................................................8-8
8.5 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8
8.5.1 Word Count .....................................................................................................................8-8
8.5.1.1 Example: 8 BPP mode...................................................................................8-8
8.5.1.2 Example: 24 BPP (packed) mode..................................................................8-9
8.5.2 Pixel End and Start..........................................................................................................8-9
8.5.2.1 4 BPP Word Layout .....................................................................................8-10
8.5.2.2 8 BPP Word Layout .....................................................................................8-11
8.5.2.3 16 BPP WORD Layout ................................................................................8-11
8.5.2.4 24 BPP mode...............................................................................................8-12
8.6 Register Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13
8.6.1 Breshenham’s Algorithm Line Draw ..............................................................................8-13
8.6.2 Example of Breshenham’s Algorithm Line Draw ...........................................................8-15
8.6.3 Block Fill Function .........................................................................................................8-16