Cirrus Logic EP93xx - Manual (Page 646)

19-4 DS785UM1
Copyright 2007 Cirrus Logic
Watchdog Timer
EP93xx User’s Guide
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READ ONLY BIT FIELDS
PLSDSN: Pulse Disable Not. The Watchdog internal PLSDIS bit
monitors the HW_PULSE_DISABLEn latch status in the
watchdog module. This provides status of the hardware
pulse duration disable function. Active low means that the
reset pulse is disabled.
OVRID: Software Override of the hardware watchdog disable. The
OVRID bit monitors the SW_OVERIDE_HW_DISABLE
register status in the watchdog module. This provides
status of the watchdog software disable overriding the
hardware disable function. This bit is active high when the
software disable is overriding the hardware disable.
SWDIS: Software Watchdog Disable. The SWDIS bit monitors the
SW_WATCHDOG_DISABLE register status in the
watchdog module. This provides status of the watchdog
software disable function. This bit is active high when the
watchdog is software disabled.
HWDIS: Hardware Watchdog Disable. The HWDIS bit monitors the
HW_WATCHDOG_DISABLEN latch status in the
watchdog module. This provides status of the watchdog
hardware disable function. This bit is active high when the
watchdog is hardware disabled.
URST: User Reset Status flip flop. Read only. When “1”, this bit
indicates that the last reset was generated by the user
reset signal (externally on RSTOn). This bit is not cleared
by any resets other than power on reset, PWR_RESETn.
3KRST: Three-Key Reset Status flip flop. Read only. When “1”, this
bit indicates that the last reset signal was generated by a
three-key reset from the key scan controller. This bit is not
cleared by any resets other than power on reset,
PWR_RESETn.
WD: Watchdog Reset Status flip flop. Read only. When “1”, this
bit indicates that the last reset was generated because of
a watch dog time out. This bit is not cleared by any resets
other than power on reset, PWR_RESETn.