Cirrus Logic EP93xx User Manual
Page 515
DS785UM1
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Copyright 2007 Cirrus Logic
SDRAM, SyncROM, and SyncFLASH Controller
EP93xx User’s Guide
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The CKE bit must be written to ‘0’ before the ClkShutdown
bit is written to ‘1’.
ReArbEn:
Re-arbitration controller Enable - Read/Write
Writing a ‘1’ to this bit allows the SDRAM Arbiter to stop
the current burst accesses to the external synchronous
memory, allow burst accesses from another requester to
begin, and later resume the stopped burst accesses. This
can suspend burst accesses from the Raster engine long
enough to deprive the display from being adequately
refreshed, and thereby cause undesired affects to appear
on the display. So, by default, this bit is ‘0’.
Writing a ‘0’ to this bit specifies that the SDRAM Arbiter
must wait for current burst accesses to complete before it
allows burst accesses from another requester to begin.
LCR:
Load FLASH Command Register - Read/Write
When Initialize = ‘0’ and MRS = ‘1’, writing a ‘1’ to this bit
allows commands to be issued to the Synchronous
FLASH device as described in
SyncFLASH Device” on page 13-8
SMEMBust:
Synchronous Memory Busy Status - Read/Write
This status bit shows that the Synchronous Memory
controller is either busy or idle:
0 - Idle
1 - Busy
When this bit is a ‘1’, writing a ‘1’ to it will clear it to ‘0’.
MRS:
Synchronous Memory Mode Register - Read/Write
When Initialize = ‘0’ and LCR = ‘0’, writing a ‘1’ to this bit
allows setup commands to be written to the Mode register
that is inside a synchronous memory device. When this bit
is written to a ‘1’, subsequent Read accesses to the
synchronous device cause commands on the AD[13:0]
pins to be written to the Mode register.
Initialize:
Initialize bit - Read/Write