Cirrus Logic EP93xx - Manual (Page 719)

DS785UM1 23-7
Copyright 2007 Cirrus Logic
Synchronous Serial Port
EP93xx User’s Guide
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23.5.8 Motorola SPI Format with SPO=0, SPH=1
The transfer signal sequence for Motorola SPI format with SPO=0, SPH=1 is shown in
Figure 23-5 , which covers both single and continuous transfers.
Figure 23-5. Motorola SPI Frame Format with SPO=0 and SPH=1
In this configuration, during idle periods:
• the SCLKOUT signal is forced LOW
• SFRMOUT is forced HIGH
• the transmit data line SSPTXD is arbitrarily forced LOW
• when the SSP is configured as a master, the SSPCTLOE line is driven LOW, enabling
the SCLKOUT pad (active LOW enable)
• when the SSP is configured as a slave, the SSPCTLOE line is driven HIGH, disabling
the SCLKOUT pad (active LOW enable).
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SFRMOUT master signal being driven LOW. The master
SSPTXD output pad is enabled. After a further one half SCLKOUT period, both master and
slave valid data is enabled onto their respective transmission lines. At the same time, the
SCLKOUT is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the
SCLKOUT signal.
In the case of a single word transfer, after all bits have been transferred, the SFRMOUT line
is returned to its idle HIGH state one SCLKOUT period after the last bit has been captured.
For continuous back-to-back transfers, the SFRMOUT pin is held LOW between successive
data words and termination is the same as that of the single word transfer.
4 to 16 bits
MS B
LS B
LS B
Q M SB Q
SSTXD
SSPOE
SSRXD
SFRMOUT /
SFRMIN
SCLKOUT /
SCLKIN