Cirrus Logic EP93xx User Manual
Page 676
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21-20
DS785UM1
Copyright 2007 Cirrus Logic
I
2
S Controller
EP93xx User’s Guide
2
1
2
1
21
0x0000_0000
Definition:
Receive left data word for channel 0.
Bit Descriptions:
i2s_rx0_left:
Receive left data word for channel 0.
I2SRX0Rt
Address:
0x8082_0044 - Read Only
Default:
0x0000_0000
Definition:
Receive right data word for channel 0.
Bit Descriptions:
i2s_rx0_right:
Receive right data word for channel 0.
I2SRX1Lft
Address:
0x8082_0048 - Read Only
Default:
0x0000_0000
Definition:
Receive left data word for channel 1.
Bit Descriptions:
i2s_rx1_left:
Receive left data word for channel 1.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
i2s_rx0_right
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
i2s_rx0_right
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
i2s_rx1_left
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
i2s_rx1_left
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