Indad – Cirrus Logic EP93xx User Manual

Page 355

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DS785UM1

9-53

Copyright 2007 Cirrus Logic

1/10/100 Mbps Ethernet LAN Controller

EP93xx User’s Guide

9

9

9

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Address:

0x8001_0050 through 0x8001_0055 - 6 Bytes - Read/Write,
when AFP = 000b, 010b or 001b

Chip Reset:

0x0000_0000

Soft Reset:

Unchanged

Definition:

Individual Address Register. There are five different Individual Addresses
accessible at offset 0x050, the Address Filter Pointer determines which one is
accessed at any one time. The first four addresses (pointer offset 0x000
through 0x011), may be used to implement destination address filters for
receive frames. The first two may also be used to qualify receive frames for
flow control processing, and the first address is used for wake-up frame
processing. The fifth address (pointer offset 0x110), is only used as the
destination address for transmit pause frames.

The least significant byte of the Individual Address corresponds to the first
byte of the address on the serial interface, with the least significant bit of the
byte corresponding to the first bit on the serial interface.

Bit Descriptions:

IAD:

Individual Address.

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

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31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

IAD

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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