Cirrus Logic EP93xx - Manual (Page 797)

DS785UM1 28-7
Copyright 2007 Cirrus Logic
GPIO Interface
EP93xx User’s Guide
2
8
2
8
28
4. EEDAT is the EEPROM data pin.
5. ROW[7:0] are the Key Matrix row pins.
6. COL[7:0] are the Key Matrix column pins.
1. IDEDA[2:0], IDECS0n, IDECS1n, and DIORn are IDE control pins.
2. DD[15:0] are the IDE data pins. DD[11:8] has no GPIO pin mapping.
3. GRLED is the Green LED pin.
4. RDLED is the Red LED pin.
5. EECLK is the EEPROM clock pin.
6. EEDAT is the EEPROM data pin.
7. ROW[7:0] are the Key Matrix row pins.
8. COL[7:0] are the Key Matrix column pins.
Table 28-3. EP9312 GPIO Port to Pin Map
Pin
Name
Default
Function
Function in
GonK
Mode
Function in
EonIDE
Mode
Function in
GonIDE
Mode
Function in
HonIDE
Mode
EGPIO[7:0] Port A Port A Port A Port A Port A
EGPIO[15:8] Port B Port B Port B Port B Port B
GRLED
3 Port E0 Port E0 Port E0 Port E0 Port E0
RDLED 4 Port E1 Port E1 Port E1 Port E1 Port E1
EECLK 5 Port G0 Port G0 Port G0 Port G0 Port G0
EEDAT 6 Port G1 Port G1 Port G1 Port G1 Port G1
SLA[1:0] Port G3:2 Port G3:2 Port G3:2 Port G3:2 Port G3:2
ROW[7:0] 7 ROW[7:0] Port C ROW[7:0] ROW[7:0] ROW[7:0]
COL[7:0] 8 COL[7:0] Port D COL[7:0] COL[7:0] COL[7:0]
IDEDA[2:0] 1 IDEDA[2:0] IDEDA[2:0] Port E7:5 IDEDA[2:0] IDEDA[2:0]
IDECS1n
1 IDECS1n IDECS1n Port E4 IDECS1n IDECS1n
IDECS0n
1 IDECS0n IDECS0n Port E3 IDECS0n IDECS0n
DIORn 1 DIORn DIORn Port E2 DIORn DIORn
DD[15:12] 2 DD[15:12] DD[15:12] DD[15:12] Port G7:4 DD[15:12]
DD[11:8]
2 DD[11:8] DD[11:8] DD[11:8] DD[11:8] DD[11:8]
DD[7:0] 2 DD[7:0] DD[7:0] DD[7:0] DD[7:0] Port H