Cirrus Logic EP93xx - Manual (Page 436)

10-42 DS785UM1
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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For a double/multiple buffer transfer, the second buffer
descriptor can be programmed while the transfer using the
first buffer is being carried out (thus reducing software
latency impact). The NFB interrupt is generated when
transfer begins using the second buffer. The NFB interrupt
service routine can then be used to update the free buffer
descriptor (in the case where a third buffer is required).
If BCRx = 0 when the transfer is triggered, then NO
transfers will occur, that is, the DMA will stay in the STALL
state.
SAR_BASEx
Address:
SAR_BASE0: Channel Base Address + 0x0018 - Read/Write
SAR_BASE1: Channel Base Address + 0x001C - Read/Write
Definition:
This register contains the base memory address from which the DMA
controller requests data.
Bit Descriptions:
SAR_BASEx: x = “0” or “1” representing the double buffer per channel.
This register contains the base memory address from
which the DMA controller requests data. At least 1 of the
SAR_BASEx registers must be programmed before the
ENABLE bit and the START bit (in the case of software-
trigger M2M mode) are set in the Control register, and also
before the corresponding BCRx register is programmed.
The second buffer descriptor can be programmed while
the transfer using the “other” buffer is being carried out
(thus reducing software latency impact). When transferring
from external device to memory, the SAR_BASEx will
contain the base address of the memory mapped device.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR_BASEx
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR_BASEx