Cirrus Logic EP93xx User Manual
Page 575
DS785UM1
15-17
Copyright 2007 Cirrus Logic
UART2
EP93xx User’s Guide
1
5
1
5
15
UART2TMR
Address:
0x808D_0084 - Read/Write
Default:
0x0000_0000
Definition:
UART SIR Loopback Register
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
0:
Must be written as “0”. Unknown During Read.
SIRTEST:
SIR test enable. Setting this bit to “1” enables the receive data
path during IrDA transmission (testing requires SIR to be
configured in full-duplex mode). This bit must be set to “1” to
enable SIR system loopback testing, when the normal mode
control register UART2Ctrl bit 7, Loop Back Enable
(LBE), has
been set to “1”. Clearing this bit to 0 disabled the receive
logic when the SIR is transmitting (normal operation). This
bit defaults to 0 for normal (half-duplex) operation.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
0
SIRTEST
0