Vicxfiqstatus, Vicxrawintr – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
Vectored Interrupt Controller
EP93xx User’s Guide
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Definition:
IRQ Status Register. The VICxIRQStatus register provides the status of
interrupts after IRQ masking.
Interrupts 0 - 31 are in VIC1IRQStatus.
Interrupts 32 - 63 are in VIC2IRQStatus.
Bit Descriptions:
IRQStatus:
Shows the status of the interrupts after masking by the
VICxIntEnable and VICxIntSelect registers. A “1” indicates
that the interrupt is active, and generates an interrupt to
the ARM Core.
VICxFIQStatus
Address:
VIC1FIQStatus: 0x800B_0004 - Read Only
VIC2FIQStatus: 0x800C_0004 - Read Only
Definition:
FIQ Status Register. The VICxFIQStatus register provides the status of the
interrupts after FIQ masking.
Bit Descriptions:
FIQStatus:
Shows the status of the interrupts after masking by the
VICxIntEnable and VICxIntSelect registers. A “1” indicates
that the interrupt is active, and generates an interrupt to
the ARM Core.
VICxRawIntr
Address:
VIC1RawIntr: 0x800B_0008 - Read Only
VIC2RawIntr: 0x800C_0008 - Read Only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FIQStatus
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIQStatus
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RawIntr
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RawIntr