Cirrus Logic EP93xx - Manual (Page 580)

16-4 DS785UM1
Copyright 2007 Cirrus Logic
UART3 With HDLC Encoder
EP93xx User’s Guide
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a 3-bit status (break, frame and parity) is pushed onto the
11-bit wide receive FIFO
• if the FIFOs are not enabled, the data byte and status are
stored in the receiving holding register (the bottom word of
the receive FIFO).
The received data byte is read by performing reads from
the UART3Data register, while the corresponding status
information can be read by a successive read of the
UART3RXSts register.
UART3RXSts
Address:
0x808E_0004 - Read/Write
Default:
0x0000_0000
Definition:
UART3 Receive Status Register and Error Clear Register. Provides receive
status of the data value last read from the UART3Data. A write to this register
clears the framing, parity, break and overrun errors. The data value is not
important.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
OE: Overrun Error.
1 - when data is received and the FIFO is already full.
0 - Cleared by a write to UART3RXSts.
The FIFO contents remain valid since no further data is
written when the FIFO is full. Only the contents of the shift
register are overwritten. The data must be read in order to
empty the FIFO.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD OE BE PE FE