Cirrus Logic EP93xx - Manual (Page 387)

DS785UM1 9-85
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
Definition:
Transmit Status Queue Current Address. The Transmit Status Queue Current
Address contains the address being used to transfer transmit status to the
queue. This register is available for debugging.
Bit Descriptions:
TSQCA: Transmit Status Queue Current Address.
RXBufThrshld
Address:
0x8001_00D0 - Read/Write
Suggested Value:
0x0080_0040
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Receive Buffer Threshold register. The receive buffer thresholds are used to
set a limit on the amount of receive data which is held in the receive data FIFO
before a bus request will be scheduled. When the number of words in the
FIFO exceeds the threshold value, the Descriptor Processor will schedule a
bus request to transfer data. The actual posting of the bus request may be
delayed due to lack of resources in the MAC, such as no active receive
descriptor.
Note: There are other reasons to schedule bus transfers other than reaching the threshold. One
of these is when an end of frame is received. The lower 2 bits of each threshold are always
zero.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
0: Must be written as “0”.
RDHT: Receive Data Hard Threshold.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD RDHT 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RDST 0 0