Txdenq, Txstsqbadd, Unchanged – Cirrus Logic EP93xx User Manual
Page 384
9-82
DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
TXDEnq
Address:
0x8001_00BC - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Transmit Descriptor Enqueue register. The Transmit Descriptor Enqueue
register is used to define the number of valid descriptors available in the
transmit descriptor queue. Only the Transmit descriptor Increment field is
writable and any value written to this field will be added to the existing
Transmit Descriptor Value. When complete descriptors are read by the MAC,
the Transmit Descriptor Value is decremented by the number read. For
example if the Transmit Descriptor Value is 0x07, and the Host writes 0x03 to
the Transmit Descriptor Increment, the new Value will be 0x0A. If the controller
then reads two descriptors, the Value will be 0x08.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
TDV:
Transmit Descriptor Value.
TDI:
Transmit Descriptor Increment.
TXStsQBAdd
Address:
0x8001_00C0 - Read/Write
Chip Reset:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TDV
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
TDI
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TSQBA
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TSQBA