Cirrus Logic EP93xx - Manual (Page 445)

DS785UM1 11-5
Copyright 2007 Cirrus Logic
Universal Serial Bus Host Controller
EP93xx User’s Guide
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scheduling the Endpoint Descriptor at the appropriate depth in the tree. The higher the polling
rate, the closer to the root of the tree the Endpoint Descriptor will be placed since multiple
lists will converge on it.
Figure 11-4 illustrates the structure for Interrupt Endpoints. The
Interrupt Endpoint Descriptor Placeholder indicates where zero or more Endpoint Descriptors
may be enqueued. The numbers on the left are the index into the HCCA interrupt head
pointer array.
Figure 11-4. Interrupt Endpoint Descriptor Structure
Figure 11-5 is a sample Interrupt Endpoint schedule. The schedule shows one Endpoint
Descriptors at a 1 ms poll interval, two Endpoint Descriptors at a 2 ms poll interval, one
Endpoint at a 4 ms poll interval, two Endpoint Descriptors at an 8 ms poll interval, two
Endpoint Descriptors at a 16 ms poll interval, and two Endpoint Descriptors at a 32 ms poll
interval. Note that in this example unused Interrupt Endpoint Placeholders are bypassed and
the link is connected to the next available Endpoint in the hierarchy.
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Interrupt
Head
Pointers
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Interrupt Endpoint Descriptor Placeholders
Endpoint Poll Interval (ms)