Cirrus Logic EP93xx - Manual (Page 81)

DS785UM1 3-11
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
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DAID: MaverickCrunch Architecture ID. This read-only value is
i n c r e m e n t e d f o r e a c h r e v i s i o n o f t h e o v e r a l l
MaverickCrunch co-processor architecture. These bits are
“000” for this revision.
HVID: Hardware Version ID. This read-only value is incremented
each time the hardware implementation of the architecture
nam ed by DA ID[2:0] is changed, t ypic ally don e in
response to bugs. These bits are “000” for this version.
ISAT: Integer Saturate Enable. This bit controls whether non-
a c c um u l a t o r i nt eg e r op e r a t i o ns , bo t h s i g n ed an d
unsigned, will saturate on overflow or underflow:
0 = Saturation enabled
1 = Saturation disabled
UI: Unsigned Integer Enable. This bit controls whether non-
accumulator integer operations treat their operands as
signed or unsigned. It also determines the saturation value
if the ISAT bit is clear:
0 = Signed integers
1 = Unsigned integers
INT: MaverickCrunch Interrupt. This bit indicates whether an
interrupt has occurred. This bit is identical to the external
interrupt signal:
0 = No interrupt signaled
1 = Interrupt signaled
AEXC: Asynchronous Exception Enable. This bit determines
whether exceptions generated by the co-processor are
s i g n a l e d s y n c h r o n ou s l y o r a s y n c h r o n o u s l y t o t h e
ARM920T. Synchronous exceptions force all data path
instructions to be serialized and to stall the ARM920T. If
exceptions are asynchronous, they are signalled by
assertion of the DSPINT output of the co-processor, which
may interrupt the ARM920T via the interrupt controller.
Enabling asynchronous exceptions does provide a
performance improvement, but makes it difficult for an
interrupt handler to determine the co-processor instruction
that caused the exception because the address of the
i n s t r u c t i o n i s n o t p r e s e r v e d . E x c e p t i o n s m a y b e
individually enabled by other bits in this register (IXE, UFE,
OFE, and IOE). This bit has no effect if no exceptions are
enabled:
0 = Exceptions are synchronous
1 = Exceptions are asynchronous