Figure 5-4. power states and transitions -11 – Cirrus Logic EP93xx User Manual
Page 137
DS785UM1
5-11
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
5
5
Figure 5-4. Power States and Transitions
5.1.6.2.1 Power-on-Reset Run
After power-on-reset, the ARM Core is automatically in run mode.
5.1.6.2.2 Run Standby Mode
Once in run mode, it is possible to move to the Standby state under these conditions:
•
A read from the Standby register location 0x8093_000C when the SHena bit in the
register is set to 1. This triggers the system to enter STANDBY mode.
•
A write to the
register.
When the SHena bit is set to 1 and the user reads the Standby register location
0x8093_000C, the EP93xx is forced to transition into the Standby state. After this transition,
the state controller will hold the Standby state before re-loading and allowing transition to the
Run state.
A write to the
register will also trigger the system to go into Standby mode.
However, the system will automatically come back to normal operation after new clock
settings take effect. The amount of time the EP93xx remains in the Standby state depends on
whether the PLL is enabled, or if the EP93xx is using the external clock. If the PLL is enabled,
the EP93xx will remain in Standby until the PLL is locked. If the EP93xx is in PLL bypass
mode (nBYP1 = 1), then the EP93xx will remain in the Standby state for One to two
16.384 kHz clock cycles. This is to ensure a minimum 'off' time. The 16.384 kHz clock,
derived from the 32.768 kHz clock, times how long the EP93xx remains in the Standby state.
When the EP93xx normally enters Standby mode, the SDRAM controller puts the external
SDRAM into self-refresh before disabling its clocks (see
“SDRAM Self Refresh” on page 13-
). This condition is only true if the refresh enable bit (RFSHEN) in the SDRAM controller is
Interrupt (if enabled) or
return from ClkSet1
Power on
Reset
Standby
Run
Halt
Write to
ClkSet1 register
Read Standby register &
SHena = 1
Any Enabled Interrupt
Read Halt register
& SHena = 1