Cirrus Logic EP93xx - Manual (Page 586)

16-10 DS785UM1
Copyright 2007 Cirrus Logic
UART3 With HDLC Encoder
EP93xx User’s Guide
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BUSY: UART Busy. If this bit is set to 1, the UART is busy
transmitting data. This bit remains set until the complete
byte, including all the stop bits, has been sent from the
shift register. This bit is set as soon as the transmit FIFO
becomes non-empty, regardless of whether the UART is
enabled or not.
DCD: Data Carrier Detect status. This bit is the complement of
the UART data carrier detect (nUARTDCD) modem status
input. That is, the bit is 1 when the modem status input is
0.
DSR: Data Set Ready status. This bit is the complement of the
UART data set ready (nUARTDSR) modem status input.
That is, the bit is 1 when the modem status input is 0.
CTS: Clear To Send status. This bit is the complement of the
UART clear to send (nUARTCTS) modem status input.
That is, the bit is 1 when the modem status input is 0.
UART3IntIDIntClr
Address:
0x808E_001C - Read/Write
Default:
0x0000_0000
Definition:
UART3 Interrupt Identification and Interrupt Clear Register. Interrupt status is
read from UART3IntIDIntClr. A write to UART3IntIDIntClr clears the modem
status interrupt. All the bits are cleared to “0” when reset.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
RTIS: Receive Timeout Interrupt Status. This bit is set to 1 if the
receive timeout interrupt is asserted. This bit is cleared
when the receive FIFO is empty or the receive line goes
active.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RTIS TIS RIS MIS