Cirrus Logic EP93xx User Manual
Page 672
21-16
DS785UM1
Copyright 2007 Cirrus Logic
I
2
S Controller
EP93xx User’s Guide
2
1
2
1
21
I2STXLinCtrlData
Address:
0x8082_0028 - Read/Write
Default:
0x0000_0000
Definition:
Line Control Data Register
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
Left_Right_Justify: Determines how the data word is justified when being
transmitted on the sdo line output.
0 - left justified.
1 - right justified
TXUF_REPEAT_SAMPLE:On TX underflow, the I
2
S controller transmits all
zeros if this bit is “1”.
If this bit is “0” the I
2
S controller repeats the last sample on
underflow.
TXDIR:
Transmit data shift direction.
0 - MSB first
1 - LSB first
I2STXCtrl
Address:
0x8082_002C - Read/Write
Default:
0x0000_0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
Left_Right_Justify
TXUF_REPEAT_SAMPLE
TXDIR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
TXUFIE
TXEMPTY_int_level