Cirrus Logic EP93xx User Manual
Page 679
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DS785UM1
21-23
Copyright 2007 Cirrus Logic
I
2
S Controller
EP93xx User’s Guide
2
1
2
1
21
RXDIR:
Receive data shift direction.
0 - MSB first
1 - LSB first
I2SRXCtrl
Address:
0x8082_005C - Read/Write
Default:
0x0000_0000
Definition:
Control Register
Bit Descriptions:
RSVD:
Reserved. Unknown During Read. Must be written as “0”.
ROFLIE:
Receive interrupt enable.
Active high
RXFull_int_level:
Rx full interrupt level select.
0 - Generate interrupt when FIFO is half full.
1 - Generate interrupt when FIFO is full.
I2SRXWrdLen
Address:
0x8082_0060 - Read/Write
Default:
0x0000_0000
Definition:
Word Length
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
ROFLIE
RXFull_int_level
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
WL
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