Cirrus Logic EP93xx - Manual (Page 582)

16-6 DS785UM1
Copyright 2007 Cirrus Logic
UART3 With HDLC Encoder
EP93xx User’s Guide
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• UART3LinCtrlMid write, UART3LinCtrlLow write and UART3LinCtrlHigh write.
To update UART3LinCtrlLow or UART3LinCtrlMid only:
• UART3LinCtrlLow write (or UART3LinCtrlMid write) and UART3LinCtrlHigh write.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
WLEN: Number of bits per frame:
11 = 8 bits
10 = 7 bits
01 = 6 bits
00 = 5 bits
FEN: FIFO Enable.
1 - Transmit and receive FIFO buffers are enabled (FIFO
mode).
0 - The FIFOs are disabled (character mode). (That is, the
FIFOs become 1-byte-deep holding registers.)
STP2: Two Stop Bits Select.
1 - Two stop bits are transmitted at the end of the frame.
0 - One stop bit is transmitted at the end of the frame.
The receive logic does not check for two stop bits being
received.
EPS: Even Parity Select.
1 - Even parity generation and checking is performed
during transmission and reception, which checks for an
even number of 1s in data and parity bits.
0 - Odd parity generation and checking is performed
during transmission and reception, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by Parity
Enable (bit 1) being cleared to 0.
PEN: Parity Enable.
1 - Parity checking and generation is enabled
0 - Parity checking is disabled and no parity bit is added to
the data frame.
BRK: Send Break.
1 - A low level is continually output on the UARTTXD
output, after completing transmission of the current
character. This bit must be asserted for at least one
complete frame transmission time in order to generate a
break condition. The transmit FIFO contents remain
unaffected during a break condition.
0 - For normal use, this bit must be cleared.