Cirrus Logic EP93xx User Manual
Page 583
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DS785UM1
16-7
Copyright 2007 Cirrus Logic
UART3 With HDLC Encoder
EP93xx User’s Guide
1
6
1
6
16
UART3LinCtrlMid
Address:
0x808E_000C - Read/Write
Default:
0x0000_0000
Definition:
UART3 Line Control Register Middle
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
BR:
Baud Rate Divisor bits [15:8]. Most significant byte of baud
rate divisor. These bits are cleared to 0 on reset.
UART3LinCtrlLow
Address:
0x808E_0010 - Read/Write
Default:
0x0000_0000
Definition:
UART3 Line Control Register Low.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
BR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
BR
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