Cirrus Logic EP93xx User Manual
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23-16
DS785UM1
Copyright 2007 Cirrus Logic
Synchronous Serial Port
EP93xx User’s Guide
2
3
2
3
23
RIE:
Receive FIFO interrupt enable:
0 - Receive FIFO half-full or more condition does not
generate the SSPRXINTR interrupt.
1 - Receive FIFO half-full or more condition generates the
SSPRXINTR interrupt.
SSPDR
Address:
0x808A_0008 - Read/Write
Default:
0x0000_0000
Definition:
SSPDR is the data register and is 16-bits wide. When SSPDR is read, the
entry in the receive FIFO (pointed to by the current FIFO read pointer) is
accessed. As data values are removed by the SSPs receive logic from the
incoming data frame, they are placed into the entry in the receive FIFO
(pointed to by the current FIFO write pointer).
When SSPDR is written, the entry in the transmit FIFO (pointed to by the write
pointer), is written. Data values are removed from the transmit FIFO one value
at a time by the transmit logic. It is loaded into the transmit serial shifter, then
serially shifted out onto the SSPTXD pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-justify
data written to the transmit FIFO. The transmit logic ignores the unused bits.
Received data less than 16 bits is automatically right justified in the receive
buffer.
When the SSP is programmed for National Semiconductor Microwire frame
format, the default size for transmit data is eight bits (the most significant byte
is ignored). The receive data size is controlled by the programmer. The
transmit FIFO and the receive FIFO are not cleared even when SSE is set to
zero. This allows the software to fill the transmit FIFO before enabling the
SSP.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA