Regi, Register descriptions pwrsts – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
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5
Register Descriptions
PwrSts
Address:
0x8093_0000 - Read Only
Definition:
The PwrSts system control register is the Power/State control register.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
RTCDIV:
The 6-bit RTCDIV shows the number of 64-seconds which
have elapsed. It is the output of the divide-by-64 chain that
divides the 64 Hz TICK clock down to 1 Hz though
showing an incrementing count. The MSB is the 1 Hz
output; the LSB is the 32 Hz output. It is reset by power-
on-reset to 000000b.
PLL1_LOCK:
PLL1 lock. This signal goes high when PLL1 is locked and
it is at the correct frequency.
PLL1_LOCK_REG:Registered PLL1 lock. This is a one-shot registered signal
of the PLL1_LOCK signal. It is only cleared on a power-
on-reset, when the device enters the Standby state or
when PLL1 is powered down.
PLL2_LOCK:
PLL2 lock. This signal goes high when PLL2 is locked, and
it is at the correct frequency.
PLL2_LOCK_REG:Registered PLL2 lock. This is a one-shot registered signal
of the PLL2_LOCK signal. It is only cleared on a power-
on-reset, when ClkSet2 is written, the device enters the
Standby state, or PLL2 is powered down.
SW_RESET:
Software reset flag. This bit is set if the software reset has
been activated. It is cleared by writing to the STFClr
location. On power-on-reset, it is reset to 0b.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CHIPMAN
CHIPID
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WDTFLG
RSVD
CLDFLG
TEST_
RESET
RSTFLG
SW_
RESET
PLL2_
LOCK_REG
PLL2_
LOCK
PLL1_
LOCK_REG
PLL1_
LOCK
RTCDIV