Cirrus Logic EP93xx User Manual
Page 630
17-34
DS785UM1
Copyright 2007 Cirrus Logic
IrDA
EP93xx User’s Guide
1
7
1
7
17
RFC:
RFC mask bit. When high, the MIR RFC status can
generate an interrupt.
RFS:
RFS mask bit. When high, the MIR RFS status can
generate an interrupt.
TAB:
TAB mask bit. When high, the MIR TAB status can
generate an interrupt.
TFC:
TFC mask bit. When high, the MIR TFC status can
generate an interrupt.
TFS:
TFS mask bit. When high, the MIR TFS status can
generate an interrupt.
MIIR
Address:
0x808B_0088 - Read Only
Default:
0x0000_0000
Definition:
MIR Interrupt Register. The IrDA interrupt is asserted if any bit in the MIIR is
high.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
RFL:
Logical AND of MIR RFL status bit and RFL mask bit.
RIL:
Logical AND of MIR RIL status bit and RIL mask bit.
RFC:
Logical AND of MIR RFC status bit and RFC mask bit.
RFS:
Logical AND of MIR RFS status bit and RFS mask bit.
TAB:
Logical AND of MIR TAB status bit and TAB mask bit.
TFC:
Logical AND of MIR TFC status bit and TFC mask bit.
TFS:
Logical AND of MIR TFS status bit and TFS mask bit.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
RFL
RIL
RFC
RFS
TAB
TFC
TFS