Cirrus Logic EP93xx User Manual
Page 673
DS785UM1
21-17
Copyright 2007 Cirrus Logic
I
2
S Controller
EP93xx User’s Guide
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21
Definition:
Transmit Control Register
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
TXUFIE:
Transmit interrupt enable. Active high
TXEMPTY_int_level:Transmit empty interrupt level select.
0 - Generate interrupt when FIFO is half empty.
1 - Generate interrupt when FIFO is empty.
I2STXWrdLen
Address:
0x8082_0030 - Read/Write
Default:
0x0000_0000
Definition:
Transmit Word Length
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
WL:
Transmit Word Length.
00 - 16 bit mode
01 - 24 bit mode
10 - 32 bit mode
I2STX0En
Address:
0x8082_0034 - Read/Write
31
30
29
28
27
26
25
24
23
22
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16
RSVD
15
14
13
12
11
10
9
8
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6
5
4
3
2
1
0
RSVD
WL
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29
28
27
26
25
24
23
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19
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RSVD
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1
0
RSVD
i2s_tx0_EN