Cirrus Logic EP93xx - Manual (Page 147)

DS785UM1 5-21
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
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PLL2_X2FBD2: These 6 register bits set the first feedback divider bits for
PLL2. On power-on-reset the value is set to 11000b (24
decimal).
Note: The value in the register is the actual coefficient minus one.
PLL2_X1FBD1: These 5 register bits set the second feedback divider bits
for PLL2. On power-on-reset the value is set to 11000b (24
decimal).
Note: The value in the register is the actual coefficient minus one.
PLL2_PS: These two bits determine the final divide function on the
VCO clock signal in PLL2.
00 - Divide by 1
01 - Divide by 2
10 - Divide by 4
11 - Divide by 8
On power-on-reset these bits are reset to 11b (3 decimal).
Note: This means that PLL2 FOUT is programmed to be 48,000,000 Hz on startup.
Note: The value in the register is the actual coefficient minus one.
PLL2_EN: This bit enables PLL2. If set, PLL2 is enabled. If this bit is
zero, PLL2 is disabled. On power-on-reset the value is set
to 0b.
nBYP2: This bit selects the clock source for the processor clock
dividers. If set, PLL2 is the clock source. If this bit is set to
zero, the external clock is the clock source. On power-on-
reset, this bit defaults to 0b.
USBDIV: These four bits set the divide ratio between the PLL2
output and the USB clock.
0000 - Divide by 1 1000 - Divide by 9
0001 - Divide by 2 1001 - Divide by 10
0010 - Divide by 3 1010 - Divide by 11
0011 - Divide by 4 1011 - Divide by 12
0100 - Divide by 5 1100 - Divide by 13
0101 - Divide by 6 1101 - Divide by 14
0110 - Divide by 7 1110 - Divide by 15
0111 - Divide by 8 1111 - Divide by 1
On power-on-reset these bits are reset to 0000b.