Cirrus Logic EP93xx - Manual (Page 154)

5-28 DS785UM1
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
5
5
A1onG: I
2
S Audio Port 1 on GPIO.
1 - I
2
S Port 1 pins are mapped to EGPIO. SDI1 is on
EGPIO[5], SDO1 is on EGPIO[4].
0 - EGPIO[5:4] are not used.
A2onG: I
2
S Audio Port 2 on GPIO.
1 - I
2
S Port 2 pins are mapped to EGPIO. SDI2 is on
EGPIO[13], SDO2 is on EGPIO[6].
0 - EGPIO[13] and EGPIO[6] are not used.
CPENA: Co-processor Enable.
1 - MaverickCrunch co-processor is enabled.
0 - C o - p r o c e s s o r i s d i s a b l e d a n d w i l l n o t a c c e p t
instructions.
U3EN: UART3 Enable.
1 - UART3 baud rate clock is active.
0 - UART3 clock is off.
MonG: Modem on GPIO.
1 - Modem support signals use EGPIO[0] pins.
0 - Modem support signals do not use EGPIO[0] pins
TonG: TENn on GPIO. This bit has no effect unless HC3EN and
HC1EN are 0.
1 - UART3 TENn signal drives EGPIO[3].
0 - EGPIO[3] used by GPIO.
GonK: GPIO on Key Matrix.
1 - Key Matrix pins are configured for GPIO operation,
0 - Key Matrix pins are controlled by other options.
The GonK has precedence over the Key Matrix controller.
T h e S P I 0 , w h e n m a p p e d t o K e y M a t r i x p i n s , h a s
precedence over GPIO. When the Key Matrix pins are
configured for SPI0, the pins unused by SPI0 can be used
for GPIO.
IonU2: IrDA on UART2.
1 - UART2 is used as an IrDA interface,
0 - UART2 is a normal UART.
D0onG: External DMA0 hardware handshake signals mapped to
EGPIO pins.
1 - Signals mapped.
0 - Signals not supported.
D1onG: External DMA1 hardware handshake signals mapped to
EGPIO pins.
1 - Signals mapped.
0 - Signals not supported.