Cirrus Logic EP93xx - Manual (Page 167)

DS785UM1 6-5
Copyright 2007 Cirrus Logic
Vectored Interrupt Controller
EP93xx User’s Guide
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TC1UI Timer Counter 1 Under Flow Interrupt. When Timer
Counter 1 has underflowed (reached zero), this interrupt
becomes active on the next falling edge of the timer’s
clock. The interrupt is cleared by writing any value to the
“Timer1Clear,” register. See Chapter 18 , "Timers" .
TC2UI Timer Counter 2 Under Flow Interrupt. When Timer
Counter 2 has underflowed (reached zero), this interrupt
becomes active on the next falling edge of the timer’s
clock. The interrupt is cleared by writing any value to the
“Timer2Clear,” register. See Chapter 18 , "Timers" .
AACINTR Advanced Audio CODEC Interrupt. See Chapter 22 ,
"AC’97 Controller" .
DMAM2P0 Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 0 Interrupt. See
Chapter 10 , "DMA Controller" .
DMAM2P1 Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 1 Interrupt. See
Chapter 10 , "DMA Controller" .
DMAM2P2 Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 2 Interrupt. See
Chapter 10 , "DMA Controller" .
DMAM2P3 Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 3 Interrupt. See
Chapter 10 , "DMA Controller" .
DMAM2P4 Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 4 Interrupt. See
Chapter 10 , "DMA Controller" .
DMAM2P5 Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 5 Interrupt. See
Chapter 10 , "DMA Controller" .
DMAM2P6 Internal Memory-to-peripheral and Peripheral-to-memory
Channel 6 Interrupt. See
Chapter 10 , "DMA Controller" .
DMAM2P7 Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 7 Interrupt. See
Chapter 10 , "DMA Controller" .
DMAM2P8 Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 8 Interrupt. See
Chapter 10 , "DMA Controller" .
DMAM2P9 Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 9 Interrupt. See
Chapter 10 , "DMA Controller" .
DMAM2M0 Memory-to-Memory (incorporating external M2P/P2M)
Channel 0 Interrupt. See
Chapter 10 , "DMA Controller" .
DMAM2M1 Memory-to-Memory (incorporating external M2P/P2M)
Channel 1 Interrupt. See
Chapter 10 , "DMA Controller" .
UART1RXINTR1 UART 1 Receive Interrupt. See Chapter 14, "UART1 With
HDLC and Modem Control Signals"